14 research outputs found
BRISC-V emulator: a standalone, installation-free, browser-based teaching tool
Many computer organization and computer architecture classes have recently started adopting the RISC-V architecture as an alternative to proprietary RISC ISAs and architectures. Emulators are a common teaching tool used to introduce students to writing assembly. We present the BRISC-V (Boston University RISC-V) Emulator and teaching tool, a RISC-V emulator inspired by existing RISC and CISC emulators. The emulator is a web-based, pure javascript implementation meant to simplify deployment, as it does not require maintaining support for different operating systems or any installation. Here we present the workings, usage, and extensibility of the BRISC-V emulator.Published versio
CodeTrolley: Hardware-Assisted Control Flow Obfuscation
Many cybersecurity attacks rely on analyzing a binary executable to find
exploitable sections of code. Code obfuscation is used to prevent attackers
from reverse engineering these executables. In this work, we focus on control
flow obfuscation - a technique that prevents attackers from statically
determining which code segments are original, and which segments are added in
to confuse attackers. We propose a RISC-V-based hardware-assisted deobfuscation
technique that deobfuscates code at runtime based on a secret safely stored in
hardware, along with an LLVM compiler extension for obfuscating binaries.
Unlike conventional tools, our work does not rely on compiling
hard-to-reverse-engineer code, but on securing a secret key. As such, it can be
seen as a lightweight alternative to on-the-fly binary decryption.Comment: 2019 Boston Area Architecture Workshop (BARC'19
Code trolley: hardware-assisted control flow obfuscation
Many cybersecurity attacks rely on analyzing a binary executable to find exploitable sections of code. Code obfuscation is used to prevent attackers from reverse engineering these executables. In this work, we focus on control flow obfuscation - a technique that prevents attackers from statically determining which code segments are original, and which segments are added in to confuse attackers. We propose a RISC-V-based hardware-assisted deobfuscation technique that deobfuscates code at runtime based on a secret safely stored in hardware, along with an LLVM compiler extension for obfuscating binaries. Unlike conventional tools, our work does not rely on compiling hard-to-reverse-engineer code, but on securing a secret key. As such, it can be seen as a lightweight alternative to on-the-fly binary decryption.Published versio
Janus: An Uncertain Cache Architecture to Cope with Side Channel Attacks
Side channel attacks are a major class of attacks to crypto-systems.
Attackers collect and analyze timing behavior, I/O data, or power consumption
in these systems to undermine their effectiveness in protecting sensitive
information. In this work, we propose a new cache architecture, called Janus,
to enable crypto-systems to introduce randomization and uncertainty in their
runtime timing behavior and power utilization profile. In the proposed cache
architecture, each data block is equipped with an on-off flag to enable/disable
the data block. The Janus architecture has two special instructions in its
instruction set to support the on-off flag. Beside the analytical evaluation of
the proposed cache architecture, we deploy it in an ARM-7 processor core to
study its feasibility and practicality. Results show a significant variation in
the timing behavior across all the benchmarks. The new secure processor
architecture has minimal hardware overhead and significant improvement in
protecting against power analysis and timing behavior attacks.Comment: 4 pages, 4 figure